Important pathways for semiconductor innovation have emerged in recent years and will continue to expand, requiring fresh approaches to collaboration and technology development. In prior decades, advancing compute performance in the chip industry was achieved primarily through 鈥渟caling鈥濃�攎iniaturizing features on a chip and accommodating more transistors onto a single piece of silicon. 鈥淢oore鈥檚 Law鈥� predicted that the number of transistors on a chip would double every two years. This model of innovation yielded remarkable benefits for decades, and the march of Moore鈥檚 Law continues. However, novel innovation frontiers hold immense promise for dramatic leaps in compute performance. These new methods push beyond Moore鈥檚 Law and appeal to 鈥渇ull stack鈥� strategies鈥� innovating across software, materials, design, architectures, and packaging鈥攁nd demand collaboration throughout the value chain.
The four programs administered through the Department of Commerce are aimed at meeting the evolving technology development needs of the semiconductor industry in the U.S. The programs have been compiled with industry input, and ongoing insights from industry are essential to ensure these programs remain most relevant to industry partners. These programs are summarized below:聽
The framework of these programs, guided by industry leaders3 and technology roadmaps, position the NAPMP, NSTC, SMART USA, and Metrology to deliver outsized and rapid impact for the nation while ensuring American dominance against global competitors in the technology race of the future. Approximate funding for these programs totals $11 billion over five years is allocated as follows:
